A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process

  • September 24, 2015
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A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process

ABSTRACT 

In this paper, we present a single-bit clock-less asynchronous delta–sigma modulator (ADSM) operating at just 0.25 V power supply. Several circuit approaches were employed to enable such low-voltage operation and maintain high performance. One approach involved utilizing bulk-driven transistors in subthreshold region with transconductance-enhancement topology. Another approach was to employ distributed transistor layout structure to mitigate the effect of low output impedance due to halo drain implants employed in today’s digital CMOS process. The ADSM achieved a characteristic center frequency of 630 Hz. It had an effective signal-to-noise-plus-distortion ratio (SNDR) of 58 dB or effective number of bits (ENOB) 9 b and just 28-nW power dissipation. A detailed analytical model capturing the effect of nonidealities of the individual circuit components is also presented for the first time with a close agreement with experimental results.

EXISTING SYSTEM:

MERGING biomedical and sensor applications operating with energy harvested from the environment require very low-voltage and low-power analog circuits. Analog-to-digital converters (ADCs), which are key building blocks in such applications, consume significant power. There is a growing trend to explore alternative architectures for analog-to-digital conversion, such as activity driven ADC [1] or clock-less asynchronous delta–sigma modulators (ADSM) [2]–[4]. ADSMs encode input signals into variation in pulse width and pulse density of the digital output, essentially providing a means for time-encoding of input analog signals [2]. No clocks are used in the design making it highly applicable to autonomous low-power sensor nodes. Compared to conventional ADC, ADSM has the advantages of being quantization-noise free with a good frequency performance needing just a first-order modulator in the loop [3], [4]

PROPOSED SYSTEM:

The proposed circuit and layout approaches were employed to realize a first-order clock-less ADSM based on Roza’s architecture [2]–[4], which is a closed-loop system consisting of an integrator and a hysteretic comparator. One implementation of the first-order ADSM is given in Fig. 1, in which a realistic comparator with time delay and a nonunitary feedback loop is implemented. In this section, we revisit the expressions for output bit stream as a function of the input signal considering the effects of all the nonidealities in the system. Such an analytical study with experimental validation has been performed for the first time-to-date.

1

Software Implementation:

  • Modelsim 6.0
  • Xilinx 14.2

Hardware Implementation:

  • SPARTAN-III, SPARTAN-VI