A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling

  • September 24, 2015
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A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling

ABSTRACT:

In this brief, a delay-locked loop (DLL)-based burst-mode clock and data recovery (BMCDR) circuit using a 4× oversampling technique is realized for passive optical network. With the help of DLL to track the input phase, the proposed circuit can recover the burst mode data in a short acquisition time and achieve large jitter tolerance. In addition, a 2.5-GHz four-phase clock generator is embedded in the chip. Implemented with a 0.18-μm CMOS technology, experiment shows that the acquisition time can be accomplished in the time of 31 bits. Incoming 2.5-Gb/s input data of 231–1 pseudorandom binary sequence, the retimed data has a root-mean-square jitter of 8.557 ps and a peakto- peak jitter of 32.0 ps, and the measured bit error rate is less than 10−10. The area of the whole chip is 1.4 × 1.4 mm2, where the BMCDR circuit core occupies 0.81 × 0.325 mm2. The total power consumption is 130 mW from a 1.8 V supply voltage.

EXISTING SYSTEM:

Passive optical networks (PONs) are a popular multiaccess network technology for deploying FTTx [1], [2]. The specification of uplink burst-mode data in ITU-T G.987.2 for 10-Gb-capable PON (XGPON) system can use asymmetric nominal line rate of 2.5 Gb/s in the upstream direction [3]. In XGPON, the clock of the optical network unit (ONU) is recovered by the downstream data from optical line terminal (OLT), and the upstream data from ONU are generated from this recovered clock. Therefore, OLT and OUN can be regarded as a single-clock source system, which may cause less frequency offset. The burst-mode frame length in XGPON is 125 μs, and the network provides the maximum split ratio at 1:64.

Each upstream slot is quite short that is less than 2 μs. As the result, the total jitter caused by frequency offset and short time slot makes the jitter tolerance range much smaller than other conventional continuous mode clock and data recovery (CDR) architectures and fast phase locking characteristics for a short acquisition time. There are different architectures of CDR circuits. The phase-locked loop (PLL)-based CDR circuits cannot be used for the burst-mode communication because of long locking time [4]–[6]. An approach using the broadband PLL can achieve fast phase acquisition, but it suffers from a tradeoff between bandwidth and jitter performance [7].

PROPOSED SYSTEM:

This brief focuses on a 2.5-Gb/s burst-mode CDR (BMCDR) circuit for XGPON. Fabricated in a 0.18-μm CMOS technology, we target at low-cost ASICs. The proposed BMCDR circuit utilizes 4× oversampling together with a fast phase-picking architecture to achieve to simultaneously track the data transition. In addition, the phase-tracking ability is achieved using an embedded delay-locked loop (DLL), which also can remove the phase error and enhance jitter tolerance for the BMCDR circuit. DLL-based CDRs are usually considered as a complexity system with dual loops or triple loops [14]–[18]. Among them, there is always a tradeoff between the tuning range and the frequency bandwidth of voltage-control delay lines (VCDLs). To decrease system complexity and design bottleneck of VCDL, combining the 4× oversampling technique with DLL not only can recovery in rapid time but also decrease the tuning range of VCDL.

 Based on the concept of multiple sampling phases to oversample each data bit, we adopt the 4× oversampling CDR architecture using a DLL for phase tracking. Through four sampling clocks to detect the data transition, Fig. 1 shows the phasor diagram of the data bit window that spans between the sampling clocks CLK0 and CLK180, and the recovered data are determined by CLK270. The DLL is utilized to track the input phase to align at the clock CLK90, and the determined clock CLK270 is in the middle of the data window when the DLL is phase-locked. With phase tracking, the CDR circuit keeps the total effective jitter below the quantization spacing of ½ bit time, i.e., 180° in a clock cycle.

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SOFTWARE IMPLEMENTATION:

  • Modelsim 6.0
  • Xilinx 14.2

HARDWARE IMPLEMENTATION:

  • SPARTAN-III, SPARTAN-VI

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