Local Seach Optimization Services

2015-16 VLSI Projects TITLES DOWNLOAD

S.No
Code
Title
Category
1
JPV1501
40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer- Coupled Technique for SerDes Interface
VLSI
2
JPV1502
A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process
VLSI
3
JPV1503
A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling
VLSI
4
JPV1504
A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes
VLSI
5
JPV1505
A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT
VLSI
6
JPV1506
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding
VLSI
7
JPV1507
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
FIR Filter
8
JPV1508
A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors
VLSI
9
JPV1509
A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory
VLSI
10
JPV1510
A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Applications
VLSI
11
JPV1511
A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator
VLSI
12
JPV1512
A New Efficiency-Improvement Low-Ripple Charge-Pump Boost Converter Using Adaptive Slope Generator With Hystere
VLSI
13
JPV1513
A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography
VLSI
14
JPV1514
A novel approach to realize Built-in-self-test(BIST) enabled UART using VHDL
VLSI
15
JPV1515
A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders
VLSI
16
JPV1516
A Novel Photosensitive Tunneling Transistor for Near-Infrared Sensing Applications: Design, Modeling, and Simul
VLSI
17
JPV1517
A Relative Imaging CMOS Image Sensor for High Dynamic Range and High Frame-Rate Machine Vision Imaging Applicat
VLSI
18
JPV1518
A Voltage Monitoring IC With HV Multiplexer and HV Transceiver for Battery Management Systems
VLSI
19
JPV1519
Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms
VLSI
20
JPV1520
Aging-Aware Reliable Multiplier Design with Adaptive Hold Logic
VLSI
21
JPV1521
Algorithm and Architecture Design of the H.265/HEVC Intra Encoder
VLSI
22
JPV1522
All Digital Energy Sensing for Minimum Energy Tracking
VLSI
23
JPV1523
An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders
VLSI
24
JPV1524
An Efficient Constant Multiplier Architecture Based on Vertical- Horizontal Binary Common Sub-expression Elimin
FIR Filter
25
JPV1525
An Efficient List Decoder Architecture for Polar Codes
VLSI
26
JPV1526
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
VLSI
27
JPV1527
Architecture for Monitoring SET Propagation in 16-bit Sklansky Adder
VLSI
28
JPV1528
Area-Efficient 3-Input Decimal Adders Using Simplified Carry and Sum Vectors
VLSI
29
JPV1529
Comparative Performance Analysis of the Dielectrically Modulated Full-Gate and Short-Gate Tunnel FET-Based Bios
VLSI
30
JPV1530
Design and Analysis of Inexact Floating-Point Adders
VLSI
31
JPV1531
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
VLSI
32
JPV1532
Design of Efficient Content Addressable Memories in High- Performance FinFET Technology
VLSI
33
JPV1533
Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging
VLSI
34
JPV1534
Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA
VLSI
35
JPV1535
Energy Consumption of VLSI Decoders
VLSI
36
JPV1536
Exact and Approximate Algorithms for the Filter Design Optimization Problem
VLSI
37
JPV1537
Fast Code Design for Overloaded Code-Division Multiplexing Systems
VLSI
38
JPV1538
Fine-Grained Access Management in Reconfigurable Scan Networks
VLSI
39
JPV1539
FPGA-Based Bit Error Rate Performance Measurement of Wireless Systems
VLSI
40
JPV1540
Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications
VLSI
41
JPV1541
Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications
VLSI
42
JPV1542
Graph-Based Transistor Network Generation Method for Supergate Design
VLSI
43
JPV1543
High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design
VLSI
44
JPV1544
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
VLSI
45
JPV1545
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processin
VLSI
46
JPV1546
Implementation of Subthreshold Adiabatic Logic for Ultralow- Power Application
VLSI
47
JPV1547
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
VLSI
48
JPV1548
Integrating Lock-Free and Combining Techniques for a Practical and Scalable FIFO Queue
VLSI
49
JPV1549
Learning Weighted Lower Linear Envelope Potentials in Binary
VLSI
50
JPV1550
Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs
VLSI
51
JPV1551
Long-Distance Measurement Applying Two High-Stability and Synchronous Wavelengths
VLSI
52
JPV1552
Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
VLSI
53
JPV1553
MAC With Action-Dependent State Information at One Encoder
VLSI
54
JPV1554
Minimum Parallel Binary Adders with NOR (NAND) Gates
VLSI
55
JPV1555
Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder
VLSI
56
JPV1556
Modulation Classification of Single-Input Multiple-Output Signals Using Asynchronous Sensors
VLSI
57
JPV1557
Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Sta
VLSI
58
JPV1558
Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System
FIR Filter
59
JPV1559
Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications
VLSI
60
JPV1560
Obfuscating DSP Circuits via High-Level Transformations
VLSI
61
JPV1561
One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes
VLSI
62
JPV1562
Partially Parallel Encoder Architecture for Long Polar Codes
VLSI
63
JPV1563
Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding
VLSI
64
JPV1564
Range Unlimited Delay-Interleaving and –Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit
VLSI
65
JPV1565
Recursive Approach to the Design of a Parallel Self-Timed Adder
VLSI
66
JPV1566
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
VLSI
67
JPV1567
Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI
VLSI
68
JPV1568
Shift Register Design Using Two Bit Flip-Flop
VLSI
69
JPV1569
Signal Design for Multiple Antenna Systems With Spatial Multiplexing and Noncoherent Reception
VLSI
70
JPV1570
Synthesis of Genetic Clock with Combinational Biologic Circuits
VLSI
71
JPV1571
Timing Error Tolerance in Small Core Designs for SoC Applications
VLSI
72
JPV1572
Two-Step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters
FIR Filter
73
JPV1573
VLSI-Assisted Non-rigid Registration Using Modified Demons Algorithm
VLSI

Our case studies

See all projects
Contact: 09952649690 / Email: jpinfotechprojects@gmail.com