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VLSI Projects 2016

2016 – 2017 VLSI IEEE FINAL YEAR Projects

A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply

Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication

RF Power Gating: A Low-Power Technique for Adaptive Radios

Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

A New Parallel VLSI Architecture for Real-Time Electrical Capacitance Tomography

Low-Power FPGA Design Using Memoization-Based Approximate Computing

Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units

A High-Speed FPGA Implementation of an RSD-Based ECC Processor

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling

Code Compression for Embedded Systems Using Separated Dictionaries

A Dynamically Reconfigurable Multi-ASIP Architecture for Multi-standard and Multimode Turbo Decoding

Design and Implementation of High-Speed All-Pass Transformation-Based Variable Digital Filters by Breaking the Dependence of Operating Frequency on Filter Order

A Mixed-Decimation MDF Architecture for Radix-2K Parallel FFT

Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolution Codes

One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements

Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers

Hybrid LUT/Multiplexer FPGA Logic Architectures

A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND-Flash Memory

Implementing Minimum-Energy-Point Systems With Adaptive Logic

High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m)

High-Performance NB-LDPC Decoder With Reduction of Message Exchange

LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter

Graph-Based Transistor Network Generation Method for Supergate Design

Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic

A Cellular Network Architecture With Polynomial Weight Functions

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks

Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device

Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors

A High Throughput List Decoder Architecture for Polar Codes

A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO

Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application

Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing

A New Binary-Halved Clustering Method and ERT Processor for ASSR System

The VLSI Architecture of a Highly Efficient  De-blocking Filter for HEVC Systems

Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals

In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

Source Code Error Detection in High-Level Synthesis Functional Verification

A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell

OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application

A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects

Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation

A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits

Low-Power Variation-Tolerant Nonvolatile Lookup Table Design

Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM

Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

A Systematic Design Methodology of Asynchronous SAR AD

Read Bit line Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs

Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs

Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence

EMDBAM: A Low-Power Dual Bit Associative Memory with Match Error and Mask Control

A Single-Stage Low-Dropout Regulator With a Wide Dynamic Range for Generic Applications

Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC

Integrated Floating-Gate Programming Environment for System-Level ICs

Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology

Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents

Statistical Framework and Built-In Self Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators

A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones

A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation

Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range

Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs

Understanding the Relation Between the Performance and Reliability of NAND Flash/SCM Hybrid Solid-State Drive

FCUDA-NoC : A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow

Optimized Built-In Self-Repair for Multiple Memories

Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest

Flexible ECC Management for Low-Cost Transient Error Protection of Last-Level Caches

Source Coding and Preemphasis for Double-Edged Pulse width Modulation Serial Communication

A High-Throughput Hardware Design of a One-Dimensional SPIHT  Algorithm

Network-on-Chip for Turbo Decoders

Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation

Speculative Look ahead for Energy-Efficient Microprocessors

A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems

Efficient Synchronization for Distributed Embedded Multiprocessors

NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices

A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies

Knowledge-Based Neural Network Model for FPGA Logical Architecture Development

Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems

A New Optimal Algorithm for Energy Saving in Embedded System With Multiple Sleep Modes

A Fast Fault-Tolerant Architecture for Sauvola Local Image Thresholding Algorithm Using Stochastic Computing

Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing

A Novel Quantum-Dot Cellular Automata X-bit ×32-bit SRAM

GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis

Ultralow-Energy Variation-Aware Design: Adder Architecture Study

An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop

Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems

Process Variation Delay and Congestion Aware Routing Algorithm for Asynchronous NoC Design

Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division

Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching

Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

On Efficient Retiming of Fixed-Point Circuits

A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register

Design of Modified Second-Order Frequency Transformations Based Variable Digital Filters With Large Cutoff Frequency Range and Improved Transition Band Characteristics

Fixed-Point Computing Element Design for Transcendental Functions and Primary Operations in Speech Processing

Trigger-Centric Loop Mapping on CGRAs

Area-Aware Cache Update Trackers for Post silicon Validation

PEVA: A Page Endurance Variance Aware Strategy for the Lifetime Extension of NAND Flash

Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures

A New CDMA Encoding/Decoding Method for on-Chip Communication Network

An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code

Concept, Design, and Implementation of Reconfigurable CORDIC

Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits

PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices

Design of a CMOS System-on-Chip for Passive, Near-Field Ultrasonic Energy Harvesting and Back-Telemetry

A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM

Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization

Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O

An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers

SRAM-Based Unique Chip Identifier Techniques

Contact: 09952649690 / Email: jpinfotechprojects@gmail.com